Germany - Laboratory equipment, optical instruments and precision equipment (except glasses)

Description

10 GBit/s Ethernet CoreTechnical Specification / License and Delivery Conditions2 SpecificationThe target technology is Globalfoundries 22FDX (22 nm FD-SOI, 22FDSOI-EXT).The Ethernet core to be procured implements all required functionalities on PHYand MAC level for the interconnection of a processor via a standard-compliant 10 Gb Ethernet interface with another IC or FPGA on a PCB. For this purpose, ermind. supports one of the following standards:10GBASE-X (10GBASE-KX4) orUSXGMIIaccording to the respective definition in IEEE Std. 802.3-2018 with a full-duplex transmission of 10 Gbps.The Ethernetcore shall preferably have a modular design, and according to the standard definition shall be divided into a MAC, a MAC-PHY interface resp. The MAC is connected to the processor via an AMBA AXI4-compatible master interface for data and an AMBA APB3 or AXI slave interface for control.The PHY contains all the necessary analog and digital circuitry to connect to theserial lanes on the board (4 lanes of 3.125 Gbps for 10GBASE-X, 1 / 2 lane(s) of 10.3125/ 5.15625 Gbps for USXGMII), i.e. the SERDES blocks, differential analog drivers, clock recovery, etc.For testing and debugging, the Ethernet core must support design-for-testability methods, e.g. build-in-self-test modules, scan chains and/or the test pattern generators defined in the IEEE802.3-2018 standard (Annex 48A or Clause 49). The delivered design shall be implementable and integrable with the following tools:- HDL synthesis: Synopsys Design Compiler or Cadence Genus- Simulation: Modelsim or Xcelium / NC-Sim- Layout: Cadence Innovus (P&R) and Virtuoso- DRC / LVS: PVS / Virtuoso, CalibreThe design shall be silicon-proven, a corresponding reference shall be provided with the offer.The standard compliant PHY-/MAC-specification is maintained over the entire temperature range from -40° to +125° C.
10 GBit/s Ethernet CoreTechnical Specification / License and Delivery Conditions1 IntroductionThe IHP is an institute of the Leibniz Association and holds a leading position worldwide in research and development of silicon-based systems, radio frequency circuits and technologies including new materials. 370 employees from 30 nations work together on innovative solutions for application areas such as wireless communication, medical technology, mobility and space travel.For the further expansion of activities in the design of highly scaled integrated digital circuits, in particular ultra-high-rate wireless communication systems and corresponding processors, common peripheral interfaces and corresponding IP cores are required.10Gb-Ethernet has been defined in the system concept as a system interface on PCB level, e.g. for connection to an on-board FPGA for signal processing. This call for tenders is intended to procure a corresponding complete Ethernet core for a processor system in 22 nm GF technology.2 SpecificationThe target technology is Globalfoundries 22FDX (22 nm FD-SOI, 22FDSOI-EXT).The Ethernet core to be procured implements all the necessary functionalities at PHY and MAC level for connecting a processor via a standard-compliant 10 Gb Ethernet interface with another IC or FPGA on a PCB. For this purpose, ermind. supports one of the following standards:10GBASE-X (10GBASE-KX4) orUSXGMIIaccording to the respective definition in IEEE Std. 802.3-2018 with a full-duplex transmission of 10 Gbps.The Ethernetcore shall preferably have a modular design, and according to the standard definition shall be divided into a MAC, a MAC-PHY interface resp. The MAC is connected to the processor via an AMBA AXI4-compatible master interface for data and an AMBA APB3 or AXI slave interface for control.The PHY contains all the necessary analog and digital circuitry to connect to theserial lanes on the board (4 lanes of 3.125 Gbps for 10GBASE-X, 1 / 2 lane(s) of 10.3125/ 5.15625 Gbps for USXGMII), i.e. the SERDES blocks, differential analog drivers, clock recovery, etc.For testing and debugging, the Ethernet core must support design-for-testability methods, e.g. build-in-self-test modules, scan chains and/or the test pattern generators defined in the IEEE802.3-2018 standard (Annex 48A or Clause 49). The delivered design shall be implementable and integrable with the following tools:- HDL synthesis: Synopsys Design Compiler or Cadence Genus- Simulation: Modelsim or Xcelium / NC-Sim- Layout: Cadence Innovus (P&R) and Virtuoso- DRC / LVS: PVS / Virtuoso, CalibreThe design shall be silicon-proven, a corresponding reference shall be provided with the offer.The standard compliant PHY / MAC specification shall be maintained throughout the temperature range of -40° to +125° C.3 License TermsThe Ethernet core shall be used in - partly externally funded - research projects of IHP. As a rule, 40 - 100 pieces of each IC design are manufactured in the MPW, whereby several manufacturing iterations for the same design are also possible within the scope of a single research project. Commercial use of the designs is not planned and can be excluded by the contractor. However, it must be possible to acquire a license for commercial use at a later date if necessary. Preferably, the customer will grant a permanent (temporally and spatially unlimited) license for use of the Ethernet core described above, limited to use in research projects. However, a license for the use in 5 research projects or 5 different IC designs (without limitation of the number of gates per design and production runs per design) is required as a minimum. In addition, a minimum of 12 months support for the integration of the Ethernet core into the IC designs must be offered within the scope of the license for each IC design. This support must already be included in the offer price. Details about the support have to be explained in the offer.4 Scope of supplyThe scope of supply for analog / integrated hard macro blocks consists of:- GDSII layout and layer mapping- LVS netlist in SPICE format + LVS report, device mapping file if required- DRC report- GTECH netlists and models for simulation- Gate-level Verilog netlist and associated SDF timing- Timing models in .lib format- Library Exchange Format (.lef) ViewFor digital modules provided on HDL basis, the scope of delivery consists of:- the RTL code (Verilog or VHDL)- synthesis and simulation scripts for the above tools- synthesis constraints (e.g. SDC format or TCL directives)- testbench incl. Testbench incl. behavioral models (in Verilog) for external components or the analog hard macros.In addition, a data sheet in PDF format is to be supplied for each module, containing the essential parameters, block diagrams of the architecture, and interface descriptions.

Opportunity closing date

26 September 2023

Value of contract

to be confirmed